Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.

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TroubleElectrical committed 2026-09-08 15:36:51 +10:00
1 parent 32eea036a8
commit 2208eb4f16
101 files changed
+4341 -10

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|lu
op[0] => Mux0.IN5
op[0] => Mux1.IN5
op[0] => Mux2.IN5
op[0] => Mux3.IN5
op[1] => Mux0.IN4
op[1] => Mux1.IN4
op[1] => Mux2.IN4
op[1] => Mux3.IN4
A[0] => Y.IN0
A[0] => Y.IN0
A[0] => Y.IN0
A[1] => Y.IN0
A[1] => Y.IN0
A[1] => Y.IN0
A[2] => Y.IN0
A[2] => Y.IN0
A[2] => Y.IN0
A[3] => Y.IN0
A[3] => Y.IN0
A[3] => Y.IN0
B[0] => Y.IN1
B[0] => Y.IN1
B[0] => Y.IN1
B[1] => Y.IN1
B[1] => Y.IN1
B[1] => Y.IN1
B[2] => Y.IN1
B[2] => Y.IN1
B[2] => Y.IN1
B[3] => Y.IN1
B[3] => Y.IN1
B[3] => Y.IN1
Y[0] << Mux3.DB_MAX_OUTPUT_PORT_TYPE
Y[1] << Mux2.DB_MAX_OUTPUT_PORT_TYPE
Y[2] << Mux1.DB_MAX_OUTPUT_PORT_TYPE
Y[3] << Mux0.DB_MAX_OUTPUT_PORT_TYPE