TroubleElectrical/FPGA_Uni
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Updated ram and rom modules so that naming is more consistent

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riley committed 2026-10-12 11:49:35 +11:00
1 parent 96ecc8553c
commit 1faa7fc3f0
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modules/ram.sv
+1 -1
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@@ -1,4 +1,4 @@
module RAM #(addrwidth=9, datawidth=5)( module rom #(addrwidth=9, datawidth=5)(
input logic [0:0] clk, input logic [0:0] clk,
input logic [2**addrwidth-1:0] addr, input logic [2**addrwidth-1:0] addr,
input logic [0:0] we, input logic [0:0] we,
modules/rom.sv
+2 -2
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@@ -1,5 +1,5 @@
module ROM #(parameter m=7,p=4) ( module rom #(parameter m=7,p=4) (
input logic [m-1:0] Ad, input logic [m-1:0] Ad,
output logic [p-1:0] Dout output logic [p-1:0] Dout
); );
@@ -16,4 +16,4 @@ module ROM #(parameter m=7,p=4) (
$readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary $readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary
`endif `endif
end end
endmodule // end ROM module endmodule // end rom module