Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni

modules/assignment2.sv

@@ -15,7 +15,7 @@
 
 module assignment2 #(width=5, ramsz=9, romsz=10) (
 	input logic [0:0] clk
-`ifdef SYNTHESIS
+`ifdef QUARTUS_SYNTH
     ,
 	input logic [4:0] HID_Register,
 	input logic [0:0] HID_PC,
@@ -77,7 +77,8 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	register_file #(width, 5) REGS (clk,
 		rd_we, (F) ? instruction[15:11] : instruction[20:16],
 		rs, instruction[25:21],
-		rt, instruction[20:16]
+		rt, instruction[20:16],
+        regs_out 
    );
     // Always use sign-extension
     logic [2**width-1:0] rt_imm;
@@ -99,6 +100,8 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 
 	// Temporary Test output
 	assign PC_Reg_Display = 16'hC342;
+
+    assign PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0];
 	
 	seven_seg_4digit display (
 		.num(PC_Reg_Display),