Updated ALU and ASU modules to conditionally require seven-segment output logic. Used for the assignment 1 demo and MUST be stripped for assignment 2.

modules/asu.sv

@@ -5,8 +5,14 @@
 module asu #(parameter width = 2)(
 	input logic [0:0] op,
 	input logic[2**width-1:0] A, input logic[2**width-1:0] B,
-   output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN,
-	output logic[7:0] out_seg_1);
+   output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN
+// Used to switch between demo mode and testbench mode
+// TODO: Strip for assignment 2
+`ifdef SYNTHESIS
+	, output logic[7:0] out_seg_1);
+`else
+    );
+`endif
 	
     logic [2**width-1:0] operand;
     always_comb begin
@@ -20,7 +26,11 @@ module asu #(parameter width = 2)(
     // Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported?
     // Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
     assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1];
-	 
-	 seven_seg dut(OUT_1, 1, out_seg_1);
+
+	// Include seven segment visual output for hardware builds only
+    // TODO: Strip this for assignment 2 outright
+    `ifdef SYNTHESIS 
+	    seven_seg dut(OUT_1, 1'b1, out_seg_1);
+    `endif
 endmodule
 `endif