Updated ALU and ASU modules to conditionally require seven-segment output logic. Used for the assignment 1 demo and MUST be stripped for assignment 2.

modules/alu.sv

@@ -9,13 +9,25 @@
 // flags[1:1] = Overflow
 module alu #(parameter width=2)(input logic [3:0] op,
     input logic [2**width-1:0] A, input logic [2**width-1:0] B,
-    output logic [2**width-1:0] OUT_1, output logic[1:0] flags,
-	 output logic [7:0] out_seg1);
+    output logic [2**width-1:0] OUT_1, output logic[1:0] flags
+`ifdef SYNTHESIS
+	, output logic [7:0] out_seg1);
+`else
+    );
+`endif
 
     logic [0:0] asu_op;
     logic [2**width-1:0] asu_out;
     logic [1:0] asu_flags;
-    asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
+    logic [7:0] asu_seven_seg_out;
+
+    // NOTE: For demo only
+    // TODO: Strip this for assignment 2
+    `ifdef SYNTHESIS
+        asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1], asu_seven_seg_out);
+    `else
+        asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
+    `endif
 
     logic [2**width-1:0] lu_out;
     lu #(width) logic_unit(op[1:0], A, B, lu_out);
@@ -35,6 +47,11 @@ module alu #(parameter width=2)(input logic [3:0] op,
             default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
         endcase
     end
-	 seven_seg dut(OUT_1, 1, out_seg1);
+
+    // NOTE: For demo only
+    // TODO: Strip this for assignment 2
+    `ifdef SYNTHESIS
+	    seven_seg dut(OUT_1, 1'b1, out_seg1);
+    `endif
 endmodule
 `endif