Added header guards to prevent errors from double-inclusions

modules/asu.sv

@@ -1,3 +1,6 @@
+`ifndef ASU_H_SV
+`define ASU_H_SV
+
 module asu #(parameter width = 2)(
 	input logic [0:0] op,
 	input logic[2**width-1:0] A, input logic[2**width-1:0] B,
@@ -15,3 +18,5 @@ module asu #(parameter width = 2)(
     // Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
     assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1];
 endmodule
+
+`endif

modules/instruction_classifier.sv

@@ -1,3 +1,5 @@
+`ifndef INSTRUCTION_CLASSIFIER_H_SV
+`define INSTRUCTION_CLASSIFIER_H_SV
 // TODO: This needs to be reworked to use manual mux-ing as to ensure low gate delay
 module instruction_classifier(input logic[5:0] op,
     output logic[0:0] R, output logic[0:0] B1, output logic[0:0] J,
@@ -14,6 +16,7 @@ module instruction_classifier(input logic[5:0] op,
             6'b00001?: OUT_1 = 7'b0000100;
             6'b000001: OUT_1 = 7'b0000010;
             6'b000000: OUT_1 = 7'b0000001;
+            default:   OUT_1 = 7'bxxxxxxx;
         endcase
 
         R  = OUT_1[6];
@@ -25,3 +28,4 @@ module instruction_classifier(input logic[5:0] op,
         M  = OUT_1[0];
     end
 endmodule
+`endif

modules/lu.sv

@@ -1,3 +1,5 @@
+`ifndef LU_H_SV
+`define LU_H_SV
 module lu #(parameter width = 2) (
     input logic [1:0] op,
     input logic [2**width-1:0] A,
@@ -14,3 +16,4 @@ module lu #(parameter width = 2) (
 		endcase
     end
 endmodule
+`endif

modules/seven_seg.sv

@@ -1,3 +1,5 @@
+`ifndef SEVEN_SEG_H_SV
+`define SEVEN_SEG_H_SV
 module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic [7:0] segments);
         always_comb begin
            case (num)
@@ -21,3 +23,4 @@ module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic
            endcase     
         end
 endmodule
+`endif

modules/shifter.sv

@@ -1,3 +1,5 @@
+`ifndef SHIFTER_H_SV
+`define SHIFTER_H_SV
 module shifter #(width=8)(input logic [2:0] op,
     input logic[width-1:0] A, input logic[width-1:0] C, input logic[$clog2(width)-1:0] B,
     output logic[width-1:0] OUT_1);
@@ -14,3 +16,4 @@ module shifter #(width=8)(input logic [2:0] op,
         endcase
     end    
 endmodule
+`endif