Removed seven segment code from alu and asu

modules/asu.sv

@@ -1,20 +1,14 @@
 `ifndef ASU_H_SV
 `define ASU_H_SV
 
-`include "seven_seg.sv"
 module asu #(parameter width = 2)(
 	input logic [0:0] op,
 	input logic[2**width-1:0] A, input logic[2**width-1:0] B,
-   output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN
-// Used to switch between demo mode and testbench mode
-// TODO: Strip for assignment 2
-`ifdef SYNTHESIS
-	, output logic[7:0] out_seg_1);
-`else
+    output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN
     );
-`endif
-	
+
     logic [2**width-1:0] operand;
+
     always_comb begin
         // A + (sub) ? B : -B
         // Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
@@ -27,10 +21,5 @@ module asu #(parameter width = 2)(
     // Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
     assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1];
 
-	// Include seven segment visual output for hardware builds only
-    // TODO: Strip this for assignment 2 outright
-    `ifdef SYNTHESIS 
-	    seven_seg dut(OUT_1, 1'b1, out_seg_1);
-    `endif
 endmodule
-`endif
+`endif