Removed seven segment code from alu and asu

modules/alu.sv

@@ -3,31 +3,19 @@
 
 `include "asu.sv"
 `include "lu.sv"
-`include "seven_seg.sv"
 
 // flags[0:0] = Cout
 // flags[1:1] = Overflow
 module alu #(parameter width=2)(input logic [3:0] op,
     input logic [2**width-1:0] A, input logic [2**width-1:0] B,
     output logic [2**width-1:0] OUT_1, output logic[1:0] flags
-`ifdef SYNTHESIS
-	, output logic [7:0] out_seg1);
-`else
     );
-`endif
     // intermediate logic for handling asu output
     logic [0:0] asu_op;
     logic [2**width-1:0] asu_out;
     logic [1:0] asu_flags;
-    logic [7:0] asu_seven_seg_out;
 
-    // NOTE: For demo only
-    // TODO: Strip this for assignment 2
-    `ifdef SYNTHESIS
-        asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1], asu_seven_seg_out);
-    `else
-        asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
-    `endif
+    asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
 
     logic [2**width-1:0] lu_out;
     lu #(width) logic_unit(op[1:0], A, B, lu_out);
@@ -47,11 +35,5 @@ module alu #(parameter width=2)(input logic [3:0] op,
             default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
         endcase
     end
-
-    // NOTE: For demo only
-    // TODO: Strip this for assignment 2
-    `ifdef SYNTHESIS
-	    seven_seg dut(OUT_1, 1'b1, out_seg1);
-    `endif
 endmodule
 `endif