From 12ae58ad865591109a17396a79a8acd0d54467d3 Mon Sep 17 00:00:00 2001
From: Riley King-Saunders <riley.kingsaunders@gmail.com>
Date: Fri, 16 Oct 2026 11:32:24 +1100
Subject: [PATCH] Removed flag assignment from within ALU OP case statement and
 instead perform it at the end. Made bit index for the ASU OP more explicit.

---
 modules/alu.sv | 26 ++++++++++++++------------
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/modules/alu.sv b/modules/alu.sv
index 4bc9398..0fe5f4b 100644
--- a/modules/alu.sv
+++ b/modules/alu.sv
@@ -15,26 +15,28 @@ module alu #(parameter width=2)(input logic [3:0] op,
     logic [2**width-1:0] asu_out;
     logic [2:0] asu_flags;
 
-    asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
+    assign asu_op = op[1];
+    asu #(width) adder_unit(asu_op, A, B, asu_out, asu_flags[0], asu_flags[1]);
 
     logic [2**width-1:0] lu_out;
     lu #(width) logic_unit(op[1:0], A, B, lu_out);
 
     always_comb begin
         case (op) 
-            4'b0000: begin OUT_1 = asu_out; flags = asu_flags; end
-            4'b0001: begin OUT_1 = asu_out; flags = asu_flags; end
-            4'b0010: begin OUT_1 = asu_out; flags = asu_flags; end
-            4'b0011: begin OUT_1 = asu_out; flags = asu_flags; end
-            4'b0100: begin OUT_1 = lu_out; flags = asu_flags; end
-            4'b0101: begin OUT_1 = lu_out; flags = asu_flags; end
-            4'b0110: begin OUT_1 = lu_out;  flags = asu_flags; end
-            4'b0111: begin OUT_1 = lu_out; flags = asu_flags; end
-            4'b1010: begin OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
-            4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
-            default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
+            4'b0000: begin OUT_1 = asu_out; end
+            4'b0001: begin OUT_1 = asu_out; end
+            4'b0010: begin OUT_1 = asu_out; end
+            4'b0011: begin OUT_1 = asu_out; end
+            4'b0100: begin OUT_1 = lu_out; end
+            4'b0101: begin OUT_1 = lu_out; end
+            4'b0110: begin OUT_1 = lu_out; end
+            4'b0111: begin OUT_1 = lu_out; end
+            4'b1010: begin OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; end
+            4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; end
+            default: begin OUT_1 = {(2**width){1'b0}}; end
         endcase
         asu_flags[2] = OUT_1 == 0;
+        flags = asu_flags;
     end
 endmodule
 `endif