From 0ef2aeeb482638e7a79443524f339d98c248b045 Mon Sep 17 00:00:00 2001
From: Riley King-Saunders <riley.kingsaunders@gmail.com>
Date: Thu, 8 Oct 2026 14:13:38 +1100
Subject: [PATCH] Added instruction counter and register file

---
 modules/instruction_counter.sv | 21 +++++++++++++++++++++
 modules/register_file.sv       | 22 ++++++++++++++++++++++
 2 files changed, 43 insertions(+)
 create mode 100644 modules/instruction_counter.sv
 create mode 100644 modules/register_file.sv

diff --git a/modules/instruction_counter.sv b/modules/instruction_counter.sv
new file mode 100644
index 0000000..2b58410
--- /dev/null
+++ b/modules/instruction_counter.sv
@@ -0,0 +1,21 @@
+`ifndef INSTRUCTION_COUNTER_H
+`define INSTRUCTION_COUNTER_H
+
+module instruction_counter #(parameter width=5)(
+    input logic [0:0] clk, input logic [0:0] we,
+    input logic [2**width-1:0] W,
+    output logic [2**width-1:0] addr
+);
+
+    logic [2**width-1:0] pc;
+    always_ff (@posedge clk) begin
+        if (we) begin
+            pc <= W
+        else
+            pc <= pc + 4;
+        end
+    end
+
+    assign addr = pc;
+endmodule
+`endif
\ No newline at end of file
diff --git a/modules/register_file.sv b/modules/register_file.sv
new file mode 100644
index 0000000..85cfa04
--- /dev/null
+++ b/modules/register_file.sv
@@ -0,0 +1,22 @@
+`ifndef REGISTER_FILE_H
+`define REGISTER_FILE_H
+
+module register_file #(parameter width=5, parameter nregs=16)(
+    input logic [0:0] clk, input logic[0:0] we,
+    input logic [$clog(nregs)-1:0] A_W1, input logic [2**width-1:0] W1,
+    input logic [$clog(nregs)-1:0] A_R1, output logic [2**width-1:0] R1,
+    input logic [$clog(nregs)-1:0] A_R2, output logic [2**width-1:0] R2
+);
+    localparam BW = 2**width;
+    logic [2**width-1:0] regs[nregs];
+
+    always_ff @(posedge clk) begin
+        if (we & (A_W1 != {(2**width){1'b0}} )) begin
+            regs[A_W1] <= W1;
+        end
+    end
+
+    assign R1 = regs[A_R1];
+    assign R2 = regs[A_R2];
+endmodule
+`endif
\ No newline at end of file