TroubleElectrical/FPGA_Uni
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Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented

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riley committed 2026-09-03 15:25:07 +10:00
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tests/tests.v
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`include "tests/seven_seg_tb.v"
`include "tests/lu_tb.v"
`include "tests/asu_tb.v"