Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented

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riley committed 2026-09-03 15:25:07 +10:00
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commit 0c21734447
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@echo off
cls
iverilog -g2012 -o testbench.vvp -I"./modules" -I"./tests" tests/tests.v
vvp testbench.vvp