Added comments to Q1 code and made submission file

Quartus/A1_Q1/seven_seg.sv

@@ -2,12 +2,12 @@
 `define SEVEN_SEG_H_SV
 
 module seven_seg(
-input logic [3:0] num, 
-input logic [0:0] rbi_inv, 
-output logic [7:0] segments);
+input logic [3:0] num,          // Input binary
+input logic [0:0] rbi_inv,      // Ripple blanking input
+output logic [7:0] segments);   // segent[0] = Ripple blanking out, segment[1] to segment[7] 7 seg LEDs
 
-	always_comb begin
-		case (num)
+	always_comb begin 
+		case (num) // implement truth table as case statement
 			4'b0000: segments = (rbi_inv) ? ~(8'b01111111) : ~(8'b00000000); // zero or blank
 			4'b0001: segments = ~(8'b00001101);
 			4'b0010: segments = ~(8'b10110111);
@@ -50,4 +50,4 @@ output logic [7:0] seg_a); // right
 	);
 
 endmodule
-`endif
+`endif